A participant with over five years of experience in BIM modeling and architectural design joined the adaptation program and continued to receive career counseling afterward. With tailored advice and support on resume writing, interviews, and workplace culture, they clarified their career direction and job search strategy. They eventually secured a position as a 3D modeling and fire protection planning engineer at a local engineering company.
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Satellite Communication System Design Technical Manager_Zhubei_06690
緯創資通股份有限公司
- 新竹縣竹北市
● Communication System Planning and Integration: Responsible for the overall planning, architecture design, specification definition, and system integration of the satellite communication system. ● RF and Antenna Technology Verification: Plan and verify RF modules and antenna interfaces, conduct link budget analysis, and ensure system performance meets mission requirements. ● Core Technology Selection and R&D Evaluation: Select RF front-end, modulation/demodulation, encoding/decoding, and digital signal processing architectures, and deeply cultivate AESA technology R&D. ● Cross-team Collaboration and Platform Integration: Collaborate with the architecture, thermal control, and testing teams to complete payload and satellite platform interface integration.
Number of clicks: 0

Thermal Transfer Engineer/A6P0 (Kaohsiung)
致茂電子股份有限公司
- 高雄市楠梓區
1. Phase change heat transfer research, heat flow simulation analysis 2. CDU (Coolant Distribution Units) design and development 3. TIM (Thermal Interface Material) research and implementation
Number of clicks: 7

G230018-Physical Design Staff/Technical Manager
創意電子股份有限公司
- 新竹市
Physical Design Staff ※ Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. 3. 3 years+ exp, have experiences in 16/12/7/5nm IC design experiences will be plus. Physical Design Manager/Technical Manager 1. Perform TOP or big-scale sub Top Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis 4. Be the block coordinator for a hierarchical design 5. Take responsibility for schedule control and awareness about critical issues 6. Training and coaching flash/junior engineers 7. 7 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus
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