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Cybersecurity Risk Analyst
瑞昱半導體股份有限公司- Hsinchu City
Job Responsibilities: 1. Perform vulnerability scanning for cybersecurity testing: Scan hosts, servers, network devices, and websites for vulnerabilities. Based on the scan results, perform: • Vulnerability risk assessment (CVSS, Critical/High/Medium rating) • False Positive (PNP) confirmation • Interpret scan results and propose remediation suggestions and improvement plans. 2. Assist the system, network, and development teams in vulnerability patching and verification. 3. Regularly compile testing result reports and track records. 4. Maintain the company's cybersecurity reputation rating. 5. Audit the vulnerability management procedures and processes of various departments. 6. Manage and maintain the cybersecurity testing platform and system. 7. Other tasks assigned by the supervisor. Qualifications: 1. Education: • Master's degree or above in Computer Science, Information Management, or related STEM fields. 2. Work Experience: • 8+ years of experience in cybersecurity, vulnerability discovery, web development, or other IT-related fields. 3. Technical Skills: • Experience in setting up and maintaining web application systems, understanding the overall web architecture (front-end, back-end, database, proxy) • Experience in setting up and maintaining actual servers (Linux, Windows, VMware, etc.) • Experience in vulnerability detection, able to collaborate with the team to patch and verify vulnerabilities • Familiarity with at least one security testing tool (OpenVAS, Greenbone, Nessus, ZAP, AppScan, Acunetix, Fortify, etc.) 4. Analytical and Problem-Solving Abilities: • Ability to effectively analyze vulnerability reports and identify vulnerabilities, and provide technical solutions. 5. Other Qualifications: • Excellent communication and collaboration skills, able to work with other technical teams and business departments. • High sense of responsibility, self-learning and problem-solving abilities, able to effectively perform tasks under pressure. Candidates with the following experience and qualifications are preferred (practical experience takes precedence over certifications): 1. Cybersecurity assessment, auditing, and intelligence gathering; 2. Cybersecurity threat hunting, identification, and incident response; 3. Certifications: CEH, Security+, CYSA+, CISSP, OSCP, ISO27001, RHCE
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Senior ISP Design Engineer, Up to Staff Level (3085250)
- Qualcomm Semiconductor Corporation_高通半導體有限公司
- Neihu District, Taipei City
【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表：https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/Senior-ISP-Design-Engineer--Up-to-Staff-Level_3085250 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 As a forward thinking technology company, Qualcomm advances the limits of innovation in Industrial and Embedded IoT to deliver next generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. We are seeking a seasoned ISP Design Engineer to join our SoC design team. In this role, you will architect and develop advanced Image Signal Processing (ISP) hardware pipelines for high performance, low power semiconductor products. You will be responsible for defining micro architectures, building performance/accuracy models, implementing hardware datapaths, optimizing PPA, and validating ISP functions that enable industry leading image quality across a wide range of products including IoT, mobile, camera centric devices, and embedded platforms. You will work closely with imaging algorithm experts, system architects, RTL designers, physical design engineers, firmware developers, and verification teams to deliver world class camera and computer vision capabilities. This role requires strong depth in imaging algorithms and practical hardware execution to translate complex IQ requirements into efficient and production ready ISP architectures. Responsibilities • Architect, design, and optimize ISP hardware modules including demosaic, noise reduction, color correction, tone mapping, sharpening, HDR merging, spatial/temporal filtering, and other image quality pipelines. • Translate imaging specifications and algorithm requirements into efficient micro architecture and hardware friendly implementations, balancing image quality with area, power, and latency constraints. • Develop C/C++/SystemC models for algorithm validation, performance estimation, bandwidth analysis, and design space exploration. • Evaluate ISP performance using KPIs such as image quality metrics, throughput, latency, memory bandwidth, and power efficiency; propose design enhancements based on quantitative data. • Collaborate with verification teams to define test plans, reference model comparisons, coverage metrics, and debugging flows for robust pre silicon validation. • Work with PD teams to meet PPA targets via pipeline design, timing closure strategies, clock/power domain planning, and architecture trade off analyses. • Support post silicon bring up, tuning, debugging, and performance correlation against pre silicon models. • Contribute to architecture documentation, programming guides, and cross team design reviews. Minimum Qualifications • Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field • Solid understanding of image signal processing algorithms and concepts (demosaic, filtering, HDR, color pipelines, noise reduction, etc.) • Strong RTL design skills (Verilog/SystemVerilog) and experience in micro architecture development and datapath design • Proficiency in C/C++/SystemC/Python for modeling, simulation, and algorithm analysis • Experience with SoC integration, memory hierarchy, bandwidth/performance estimation, and low power design techniques • Ability to work cross functionally and deliver designs from concept to silicon Preferred Qualifications • Experience implementing ISP pipelines or image quality algorithms in hardware as seen in roles such as Camera Engineer, Camera Senior Engineer or Camera Staff Engineer • Background in computational photography, multi frame fusion, CV workloads, or ML based IQ algorithms • Familiarity with sensor pipelines, 3A (AWB/AEC/AF), tuning workflows, or camera system integration • Nice to have experiences in scripting language. • Nice to have experiences in FPGA flow
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High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS)(3085251) (Hsinchu, Taipei)
- Qualcomm Semiconductor Corporation_高通半導體有限公司
- Neihu District, Taipei City
【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表：https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/High-Speed-IP-Integration-Engineer--Up-to-Snr-Staff--USB-PCIe-UHS---Hsinchu--Taipei-_3085251 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 work location: Hsinchu / Taipei As a forward-thinking technology company, Qualcomm advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. We are seeking a seasoned RTL Design Engineer to join our SoC design team. In this role, you will be responsible for architecting and implementing RTL designs for complex SoC platforms, with a focus on integration and performance evaluation of 3rd party IPs such as USB and PCIe. You will collaborate closely with verification, physical design, and system architecture teams to ensure seamless integration, robust functionality, and optimal performance. Responsibilities • Define and implement RTL architecture for SoC subsystems • Integrate 3rd party IPs (USB, PCIe, UHS) into SoC designs and evaluate their performance • Develop and optimize RTL code for performance, power, and area efficiency • Collaborate with verification teams to ensure functional correctness and coverage • Work with physical design teams to achieve timing closure and DFT compliance • Debug and resolve RTL issues across simulation, emulation, and silicon validation • Drive methodology improvements and automation for RTL design flow • Provide guidance on coding styles, interface protocols, and best practices • Occasional business travel across APAC and other regions may be required Minimum Qualifications • Master’s degree in Electrical Engineering, Computer Engineering, or related field • 5+ years of hands-on experience in RTL design and SoC integration • Proficiency in Verilog/SystemVerilog and RTL design methodologies • Experience with integration and performance evaluation of USB / PCIe / UHS 3rd party IPs • Familiarity with RTL-to-GDSII flow and timing closure • Strong scripting skills in Python, Tcl, or Shell • Excellent problem-solving and cross-functional communication skills Preferred Qualifications • Experience with low-power design techniques and clock/power domain crossing • Knowledge of AMBA protocols (AXI, AHB, APB) and interconnect design • Familiarity with post-silicon validation and debug of interface IPs • Exposure to EDA tools such as Synopsys Design Compiler, VCS, or Cadence tools • Comfortable working in a globally distributed engineering environment • Experience correlating pre-silicon verification with post-silicon performance/yield
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SoC Front-End Integrator, Senior to Staff (Hsinchu, Taipei)(3085252)
- Qualcomm Semiconductor Corporation_高通半導體有限公司
- Neihu District, Taipei City
【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表：https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/SoC-Front-End-Integrator--Senior-to-Staff--Hsinchu--Taipei-_3085252-1 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 work location: Hsinchu / Taipei Job Description As a forward-thinking technology company, Qualcomm advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. We are seeking a seasoned SoC Front-End Integrator to join our SoC design team. In this role, you will be responsible for integration of RTL/IP blocks and ensuring efficient communication across internal modules within complex SoC platforms. The position emphasizes chip-level interconnect, subsystem integration, and interface consistency, ensuring robust functionality, timing closure, and seamless collaboration between different design teams. Responsibilities • Integrate RTL and internal IP blocks into SoC designs • Ensure efficient communication and data flow between internal subsystems (e.g., CPU, memory, interconnect, peripherals) • Handle bus/interconnect design (AXI, AHB, APB) and optimize subsystem connectivity • Manage clock/reset domain crossing (CDC/RDC) to ensure reliable synchronization • Collaborate with verification teams to validate subsystem interactions and coverage • Work with physical design teams to achieve timing closure and integration readiness • Debug and resolve integration issues across simulation, emulation, and silicon validation • Support system-level bring-up and performance correlation in post-silicon validation • Drive methodology improvements and automation for SoC integration flow • Provide guidance on interface protocols, integration best practices, and coding styles • Occasional business travel across APAC and other regions may be required Minimum Qualifications • Master’s degree in Electrical Engineering, Computer Engineering, or related field • 5+ years of hands-on experience in SoC front-end integration • Proficiency in Verilog/SystemVerilog and SoC integration methodologies • Strong understanding of chip-level communication protocols and subsystem interaction • Familiarity with RTL-to-GDSII flow and timing closure • Strong scripting skills in Python, Tcl, or Shell • Excellent problem-solving and cross-functional communication skills Preferred Qualifications • Experience with low-power design techniques and clock/power domain crossing • Knowledge of AMBA protocols (AXI, AHB, APB) and interconnect design • Familiarity with post-silicon validation and debug of subsystem communication • Exposure to EDA tools such as Synopsys Design Compiler, VCS, or Cadence tools • Comfortable working in a globally distributed engineering environment • Experience correlating pre-silicon verification with post-silicon performance/yield
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Digital IC Design Engineer (Tainan)
- 奇景光電股份有限公司
- Xinshi District, Tainan City
1. Planning or assistance related to ARM-based SoC integration. 2. Development of peripheral IP for SoCs with AMBA (AHB/APB/AXI) interfaces. 3. Familiarity with digital logic design and Verilog RTL coding. 4. Requires domestic and international travel.
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Senior Electronics Engineer ~ Welcome to those who have returned to their hometowns after working in Beijing.
- 建準電機工業股份有限公司
- Qianzhen District, Kaohsiung City
1. Electronic and circuit evaluation and loop design for new motor projects. 2. Providing technical assistance and solutions in electronics and communications. 3. Prototype sample production and circuit board testing. 4. Developing new electronic components and conducting related testing and verification.
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[2026 Pre-employment and R&D Alternate Service] AI Algorithm R&D Engineer - Kaohsiung Office - R08
- 友達光電股份有限公司
- Qianzhen District, Kaohsiung City
AU Optronics' Kaohsiung Software Solutions R&D Center cordially invites you to join us and become a key driver of next-generation AI technology! We are looking for AI algorithm R&D engineers to work with our top AI team to advance the company's research capabilities in underlying AI models. Beyond simply optimizing AI, you will delve into algorithm design and development, bringing cutting-edge technologies to the company and contributing to academic research as an AI researcher! If you also wish to develop your career in Kaohsiung and stay abreast of the forefront of AI technology, please apply and contact us for further details! 【Job Responsibilities】 1. AI Algorithm Design and Development: Responsible for the design, training, optimization, and performance evaluation of image recognition-related models. 2. AI-Driven Control Flow and Optimization: Researching how to utilize AI algorithms (such as reinforcement learning, model predictive control, and other potential technologies) to replace or improve the efficiency of existing processing flows. 3. Data Analysis and Visualization: Performing feature engineering and analysis on multi-dimensional tabular data or image data to transform it into effective training input. 4. Cutting-Edge Technology Transfer: Tracking and evaluating the latest research papers and technologies in the AI field and attempting to apply them to solve practical control or recognition problems. 5. Academic output: Participate in the writing of technical reports, patent applications, or publication of AI papers in journals. 【Skills Required】 Essential Qualifications: 1. Strong Python programming skills, proficient in deep learning frameworks such as PyTorch or TensorFlow. 2. Familiar with computer vision technologies (e.g., object detection, image segmentation, feature extraction). 3. Solid foundation in mathematical modeling, optimization theory, or numerical analysis. 4. Problem-solving ability, capable of generating and experimentally verifying algorithms for non-standardized problems (e.g., control flow optimization). 5. Ability to research new methods; experience in publishing AI-related papers is preferred. The following experience is especially valuable: 1. System development capabilities, familiar with FastAPI/Flask or related backend framework design experience. 2. Familiar with basic Docker operations, and experience in building development and deployment environments. 3. Practical experience in deploying models to NPUs or Edge AI devices. 4. Experience in reinforcement learning or optimized control related projects is preferred.
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[Technology R&D] Micro LED Panel Design Engineer - Hsinchu Plant - R07
- 友達光電股份有限公司
- Hsinchu City
【Job Responsibilities】 1. Micro LED Panel Circuit and Backplane Design 2. Micro LED Panel Issue Analysis and Solution Delivery 3. Micro LED Panel Quality and Reliability Improvement 4. Touch Panel Design with Micro LED 【Job Requirements】 1. Prior knowledge of semiconductor components and circuitry is preferred. 2. Previous experience in the panel industry is preferred.
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[2026 Pre-employment and R&D Alternate Service] Automation Equipment Software Development Engineer (Newcomers Only) - Taichung Plant - R10
- 友達光電股份有限公司
- Xitun District, Taichung City
Passionate about image processing, AI technology, or automation systems? Want to showcase your expertise in advanced manufacturing? Join us and build state-of-the-art automated inspection solutions! 【Job Responsibilities】: 1. Develop automated inspection software for large-scale AOI systems such as Array/CF/MicroLED. 2. Must understand image processing principles and algorithm development. 3. Must have experience in software development such as VB, VC++, OpenCV, CUDA, etc., and be familiar with AI Agent Co-Work. 4. Experience with Python/Tensorflow/AI development is a plus. We are looking for: - 2026 graduates - Fresh graduates from Electrical and Electronic Engineering/Computer Science related majors. Early Bird Offer: │Early bird resumes will receive priority review.│Enhance your resume's visibility and get noticed by managers first!
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【SMAI】SR DATA SCIENTIST, SMART MFG & AI (Taoyuan/Taichung)
- 台灣美光
- Houli District, Taichung City
Apply here: https://careers.micron.com/careers/job/38509186 As a Data Science Engineer at Micron, you will employ techniques and theories drawn from areas of mathematics, statistics, semiconductor physics, materials science, and information technology to uncover patterns in data from which predictive models, actionable insights, and solutions can be developed. You will interact with experienced Data Scientists, Data Engineers, Business Areas Engineers, and UX teams to identify questions and issues for data analysis projects and improvement of existing tools. In this position, you will help develop software programs, algorithms and/or automated processes to cleanse, integrate, and evaluate large datasets from multiple disparate sources. There will be significant opportunities to perform exploratory and new solution development activities. Required qualification: • B.S./M.S. degree or equivalent experience in Data Science, Computer Science, Industrial Engineering or other engineering field. PHD in related subject areas are preferred. • At least 3 year experience in data science in engineering or related industry with in-depth knowledge in statistical modeling, machine learning, deep learning. Strong skills in python and at least familiar with 1 machine learning framework(like pyTorch, sklearn etc.). • Ability to extract data from different databases via SQL and other query languages and applying data cleansing, outlier identification, and missing data techniques. Experience working in Google cloud platform or other big data platform is a plus. • Strong skills to quickly build prototype solutions based on business requirements, experience deploying data science solution into production environments. • Excellent communication skills for explaining models, assumptions, and results to non-technical stakeholders, able to work independently with internal and external stakeholders to drive ideas to resolution. • Proactive problem-solving approach and ownership mindset. • Passion and interest to learn semiconductor manufacturing to deal with terabytes and petabytes of data to solve memory wafer related problems, enjoy working in diverse environment. Preferred qualification: • Experience with Generative AI solutions including RAG, LLM tuning, agentic problem solving. Solid experience with RCA (root cause analysis) related algorithms and modeling in solving complex industry problems are preferred. . • Good full stack skills to build end-to-end data science application with scalability and robustness is preferred. • Experience working with Manufacturing Execution Systems (MES), or good knowledge in wafer process and yield analysis is a plus • Existing papers from CVPR, NIPS, ICML, KDD, and other key conferences are plus, but this is not a research position.
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