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[2026 R&D Alternate Service] IP Front End Engineer (Hsinchu)
M31 Technology Corporation_円星科技股份有限公司- Zhubei City, Hsinchu County
【Become a Member of Ensei】 Founded in 2011 by a group of professional and passionate partners, Ensei Technology is a rising star in the integrated circuit silicon intellectual property design service industry. Upholding the vision of "becoming the most trusted IP company in the semiconductor industry," we pursue sustainable operation and growth. We sincerely welcome you to become a member of Ensei, join us, and stand on the international stage! Let's work together to create value and pursue excellence with a culture of quality! 【Job Description】 The main business of M31 is licensing IP to IC design companies and wafer foundries. This position is a research and development alternative role for a Front-end Engineer responsible for the IP design process. 【Job Responsibilities】 1. Develop CAD utility for design automation: - Library characterization of SRAM/STD timing, power, and quality assurance. - SRAM compiler design, GDS tilling, netlist tilling. - Support RD to fix EDA issues. 2. Benchmarking and evaluation: - Work closely with a standard cell design team to optimize performance, power, and area. - Familiar with P&R tools (ICC/Innovus). 3. Experience in script programming: - Linux shell/TCL/Perl script. 【Requirements and Qualifications】 1. Master's degree or above in Electronics, Electrical Engineering, Telecommunications, Electrical Control, Computer Science, or related fields. 2. Proficient in: Various IC design automation tools; C, C++, TCL, CSH, Perl, and other programming languages. 3. Programming ability. 4. Applicants should attach: - Photo, resume, and personal statement; - Abstracts of papers (research topics, advisor's name, field of expertise, awards); - University and graduate school transcripts.
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[2026 R&D Alternate Service] IO R&D Engineer (Hsinchu)
- M31 Technology Corporation_円星科技股份有限公司
- Zhubei City, Hsinchu County
【Become a Member of Ensei】 Founded in 2011 by a group of professional and passionate partners, Ensei Technology is a rising star in the integrated circuit silicon intellectual property design service industry. Upholding the vision of "becoming the most trusted IP company in the semiconductor industry," we pursue sustainable operation and growth. We sincerely welcome you to become a member of Ensei, join us, and stand on the international stage! Let's work together to create value and pursue excellence with a culture of quality! 【Job Description】 The main business of M31 is licensing IP to IC design companies and wafer foundries. This position is a replacement position responsible for R&D related to IO circuit design. 【Responsibilities】 1. I/O circuit design 2. High-speed I/O circuit design 3. I/O/ESD/Latch-Up Design and Check 4. Basic/Advanced knowledge of PISI, ESD, and I/O 【Requirements and Qualifications】 1. Master's degree or above in Electronics, Electrical Engineering, Telecommunications, Electrical Control, Computer Science, or related fields. 2. Circuit simulation, ESD design and debugging. 3. Familiar with Virtuoso and Hspice. 4. Applicants should attach: - Photo, resume, and personal statement - Abstracts of papers (research topics, advisor's name, field of expertise, awards) - University and graduate school transcripts
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Chief Engineer of Process Development
- 瑞儀光電股份有限公司
- Qianzhen District, Kaohsiung City
1. Collect industry process technologies and theoretical research. 2. Study material properties and corresponding processes. 3. Plan process methods for new products. 4. Transform process technologies into production capabilities. 5. Evaluate and develop process equipment.
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CS - EUV F22 System Lead – Kaohsiung _ J-00330478
- (ASML)台灣艾司摩爾科技股份有限公司
- Zuoying District, Kaohsiung City
The role of the System lead is to independently plan, prep, verify, merge and execute service actions sequences into the most efficient and effective method/sequence. The role encompasses the preparation of the sequences collected from ARE and Coach databases. This person has a continuous improvement mindset and will communicate internally within the OPP team. Provide insights for the scheduling in relation to the sequences. They are in frequent communication with the central sequence integration team. Education and experience BS/MS major in Mechanical, Electrical/ Electro-optical, Controlling Engineering,/ Photonics, Physics or other related field Skills Good communication skill Basic English skill Cost awareness Logic think and well planning This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology. Inclusion and diversity ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.
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DRAM Bus and PDN Designer, up to Sr. Staff (3081816)
- Qualcomm Semiconductor Corporation_高通半導體有限公司
- Hsinchu City
【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508110 【Job Overview】 The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design bus circuits and power distribution network for the custom DRAM to improve system KPIs such as bandwidth, latency, power, and thermal. The candidate will work on solutions of high-speed and high-bandwidth bus design for advanced memory. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. 【Responsibilities】 -Develop and optimize circuits for high-bandwidth memory bus and PDN control, timing, and control -Analyze and ensure the integrity of signals on the bus and PDN across PVT corners -Develop and validate the bus behavior for various access protocols to meet throughput, latency, and energy specifications -Develop novel fabrics for best/robust distribution of high-bandwidth busses and PDN across the DRAM array, compute, and IO -Create layouts that optimize the bus and PDN placement for routability across the whole chip -Use state-of-the-art design and simulation tools to simulate the bus behavior and manufacture readiness -Develop behavioral, timing, and power models of the bus to guide the architecture choices across AI, compute, and mobile workloads -Develop power modeling framework to build state-dependent power and determine PMIC requirements -Floorplan 3D DRAM chips under 3D integration manufacturing constraints, testability, repairability, and high performance
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DRAM Circuit Designer, up to Sr. Staff (3081820)
- Qualcomm Semiconductor Corporation_高通半導體有限公司
- Hsinchu City
【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508109 【Job Overview】 The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. 【Responsibilities】 • Design and optimize memory core circuits for higher sense margin, improved array timing, area • Develop and optimize DRAM circuits and timing control for performant, area, and energy efficient cell array • Develop bank array placement strategies across various bank array, TSV, and power distribution choices • Develop novel fabrics for best/robust distribution of high-bandwidth busses across the DRAM array, compute, and IO • Create layouts that optimize circuit placement, signal routing, and power delivery • Develop robust power delivery to the array design • Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness • Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads • Floorplan DRAM circuits under manufacturing constraints, testability, repairability, and high performance
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3D DRAM Architecture, up to Sr. Staff (3081821)
- Qualcomm Semiconductor Corporation_高通半導體有限公司
- Hsinchu City
【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508019 【Job Overview】 The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. 【Responsibilities】 • Develop and optimize 3D DRAM bank organization and near-memory computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W •Develop and validate models for 3D DRAM performance, power, and yield as function of bank, TSV, and power distribution choices •Develop novel fabrics for best/robust distribution of high-bandwidth data from 3D DRAM memory arrays to the near-memory computing units across various workloads for mobile, compute, and XR applications •Develop power distribution topology that enable robust DRAM operation in the 3D stack •Simulate and emulate system performance of 3D DRAM architecture choices across AI, compute, and mobile workloads •Floorplan 3D DRAM chips and design memory array control structures under 3D integration manufacturing constraints, testability, repairability, and high performance
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DRAM PHY Designer, up to Sr. Staff (3081815)
- Qualcomm Semiconductor Corporation_高通半導體有限公司
- Hsinchu City
【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508111 【Job Overview】 The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. 【Responsibilities】 • Architect, design, and implement high-speed PHY circuits • Create layouts that optimize circuit placement, signal routing, and power delivery • Develop robust power delivery to the PHY design • Simulate signal integrity and SNR performance together with the package and board s-parameter model • Simulate pre-layout and post-layout mixed-mode circuits under PVT corners • Incorporate power management features to reduce energy consumption • Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness • Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads • Floorplan PHY circuits under manufacturing constraints, testability, repairability, and high performance
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Software R&D Director
- 泰科動力股份有限公司
- Linkou District, New Taipei City
1. Familiar with robotics-related technologies and software development. 2. Possesses industry foresight and team leadership and management skills. 3. Has strong overall planning, product development, and technology planning abilities. 4. Prior experience managing a brand company team is preferred.
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[Xinzhuang Headquarters] [Welcome outstanding recent graduates to join us] Thermal Engineer
- 勤誠興業股份有限公司
- Xinzhuang District, New Taipei City
1. System thermal planning and evaluation; 2. System thermal simulation analysis and verification; 3. System thermal experimental testing; 4. Research and solution of thermal problems; 5. Assistance with thermal-related issues in product development.
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