A participant with over five years of experience in BIM modeling and architectural design joined the adaptation program and continued to receive career counseling afterward. With tailored advice and support on resume writing, interviews, and workplace culture, they clarified their career direction and job search strategy. They eventually secured a position as a 3D modeling and fire protection planning engineer at a local engineering company.
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Senior Switch Hardware Design Engineer - Work Location: Hsinchu
優達科技股份有限公司
- 新竹縣竹北市
1. Ethernet Switch hardware design, debug, evaluation, and verification 2. Responsible for PCB material selection (SI/PI considered), schematics design, PCB layout constraint & review, HW DVT test and 2nd source verification...etc. 3. Writing and maintaining the hardware specification of the projects, failure analysis report if needed 4. Study tools & instruments for design & validation
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Full-stack Engineer (AI) _ Hsinchu _ 04895
緯創資通股份有限公司
- 新竹市
Please submit your application through the Wistron official website: https://jobs.wistron.com/#/app. Resumes submitted through the official website will be reviewed first. Please register an account with your personal email address so we can contact you later. Thank you! About the Job: You will be joining a rapidly growing AI department. With the increasing demand for AI model solutions, we are expanding our team and seeking a passionate full-stack engineer to develop highly interactive applications and scalable backend systems to meet diverse needs. Here, you will have the opportunity to expand your technical expertise and be deeply involved in the development and deployment of Large Language Model (LLM) applications, showcasing your technical talents. Job Description: As a full-stack engineer, you will play a key role in designing, developing, and maintaining the front-end and back-end of applications. Your responsibilities include: • Creating user-friendly web interfaces • Developing robust backend APIs • Integrating AI and LLM (such as ChatGPT, Google Gemini) into applications • Ensuring smooth deployment and service integration, and optimizing system performance. If you are proactive, a good team player, have excellent problem-solving skills, and are passionate about generative AI and large language model (LLM) technologies, we look forward to meeting you! Job Responsibilities: • Package AI and LLM models into applications or APIs, and be responsible for deployment and launch. • Develop and optimize Retrieval-Augmented Generation (RAG) technology to improve the quality of LLM responses. • Design and optimize LLM Prompt Engineering to improve the accuracy and usability of AI responses. • Collaborate with AI research teams to deploy ChatGPT, Google Gemini, and other LLMs in application systems. • Develop RESTful APIs to support AI model inference and data retrieval. • Assist in optimizing system performance to ensure stability and scalability. • Collaborate with cross-departmental teams to integrate technologies and solve problems according to project requirements. Professional Skills Required: • Python (Flask / FastAPI) • Docker (application containerization deployment) • RESTful API development • SQL / NoSQL databases (PostgreSQL, MongoDB) • Git (version control) • LLM APIs (such as OpenAI API, Google Gemini API) • Prompt Engineering (AI instruction design and optimization) • RAG technology (retrieval enhancement generation) Bonus Points: • GitLab CI/CD • Linux Syntax • Node.js • React.js / Next.js • Kubernetes (Container Management) • OpenGL / WebGL • PyTorch / TensorFlow (Deep Learning Frameworks) • OpenCV (Computer Vision) • Cloud Platform Experience (AWS, GCP, Azure) • Familiarity with AI Agents and Vector Databases (such as FAISS, Weaviate)
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【2026 Summer Intern】Digital IC Design Engineer
聯詠科技股份有限公司
- 新竹縣竹北市
2026 Novatek Summer Internship Program Program Features: challenging tasks, employment opportunities, guidance from mentors, social events, accommodation allowance Location: Hsiuchu Science Park or Zhubei City Internship Period: 2026/7~2026/8 Weekday (Mon.~Fri.) Job Description: Support DV & Show Picture Environment Enhancement Process the basic Frond-End design task Design, analysis, and HDL (Verilog/System Verilog) coding Summarize the findings of papers and patents Requirements: Knowledge of VLSI, digital IC design and basic IC flow is a must. Knowledge of Verilog or System Verilog is required. Familiar with C code、Python、UVM、Spyglass Knowledge of Python, PERL or TCL is a plus. Qualifications: 1.Pre-graduate students (Currently undergraduates 4th year) or Master’s or Ph.D. students in Electrical Engineering, Computer Science or related field 2. Interested candidates should first get the permission from their professors to attend internship program 3. Please also provide the following documents: Resume/CV Educational transcripts/research or thesis topics
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